Ivris B. Raymond

• Advisor: Ronald G. Dreslinski

• GPA: 4.0
• Honors Thesis: Digital Simulations of Memristors Towards Integration with Reconfigurable Computing

A collaborative effort between several faculty and students at the University of Michigan to provide education on semiconductor design, manufacturing, and applications of semiconductors (control systems, AI, etc.) to high school students.

• Gave lectures introducing students to a wide variety of topics in embedded system programming, computer architecture, and ML.
• Developed some instructional material for this initiative. Some material I developed is available online at arenile.github.io/hotis-docs-site.

• Designed hardware for an OBD-II interface device and assisted in implementing an RTOS for this device.

• Identified communication and reporting issues in diagnostic software and architected a holistic dashboarding solution for reporting these issues in third-party software. This solution provides a usable problem notification and identification mechanism to Analysts with non-technical backgrounds.
• Implemented a stop-gap solution for catching these problems until the long-term solution is able to be implemented by the development teams.

GLEAM is a processing-near-memory accelerator for Graph Neural Networks (GNNs) that achieves up to a 10× speedup by leveraging a bank-level processing unit to perform partial aggregations near memory.

• I designed the GLEAM architecture and performed the theoretical analysis of its performance along with the area analysis.
• I handled most of the graph data preparation for benchmarks that were run to evaluate GLEAM’s performance.

With the rising adoption of ML for design space exploration, current approaches to simulating designs with meaningful fidelity have become a substantial bottleneck for the number of designs that ML-based approaches can evaluate when exploring the design space. This project examines whether world models may offer a faster alternative to traditional approaches to detailed microarchtiectural simulation while maintaining enough fidelity to converge on good designs.

• Designing a transformer-based world model for microarchitectural state capable of modeling how execution of a given workload affects state across various microarchitectural configurations.
• Conducted a motivational study on the need for faster simulators to support emerging ML-based techniques for design space exploration in computer architecture.

Computing systems in high-reliability deployments are often qualified for those deployments at system-level granularity while failures often occur at subsystem-level. Obsolescence poses a high risk to systems of this manner, as failing components often necessitate a complete system redesign or at least re-qualification, which is itself expensive and time-consuming. This project examines whether LLMs can be used to ease this burden by engineering drop-in replacements for failing, obsolete digital components based on the behavior of the original component and the broader design specifications of the system.

• Implemented an agent orchestration system designed to support LLM-based agents in writing RTL for obsolete digital components with hierarchical structure to improve legibility for human engineers.
• Designed and implemented a Retrieval Augmented Generation (RAG) system to provide additional context based on existing system documentation and the functional behavior of the obsolete digital component.

Current LLMs often leverage Expert Parallelism to improve inference throughput. This poses challenges for routing tokens between physical devices while also batching effectively for throughput optimization, particularly for long context inputs. We applied a graph-based algorithm in this project and measured its effectiveness for routing tokens among physical devices assuming a model was deployed using expert parallelism.

Many existing tools for memory tracing and bug detection rely on dynamic program analysis. For this project, we implemented ideas presented in Spindle (Wang, et al.) to perform memory tracing and bug detection using static analysis, achieving constant execution time and trace size scaling with array element count compared to the increasing time and size scaling of tools like Intel Pin and Valgrind. Our implementation is available on GitHub at github.com/EECS-583-Group-4/final-project.git.

Developed an autonomous vehicle capable of navigating around a track of reflective tape using two simple light sensors using an FPGA board. The system implemented a MicroBlaze SoC on the FPGA and utilized the FreeRTOS Kernel for scheduling.

Conducted a survey of various techniques for rowhammering and their implementation schemes, then produced a report on how a synthesis of new techniques may be capable of breaking some of the finalists in the NIST PQC Standardization Process by serving as the fault-injection mechanism.

Analyzed the power usage characteristics of a microcontroller performing AES encryptions across a variety of AES implementations. These implementations used many variations and combinations of masking and hiding techniques to improve their resiliency against power analysis attacks.

ML training, particularly for transformer-based world models

CPU microarchitecture simulation

Building applications that apply LLM agents and RAG

Constructing compiler passes for static analysis of workload characteristics

Implementing real-time 3D rendering engines