Project on Ivris Raymond

World Models for Microarchitectural Design Space Exploration

Fri, 01 May 2026 00:00:00 +0000

Overview

With the rising adoption of ML for design space exploration, current approaches to simulating designs with meaningful fidelity have become a substantial bottleneck for the number of designs that ML-based approaches can evaluate when exploring the design space. This project examines whether world models may offer a faster alternative to traditional approaches to detailed microarchtiectural simulation while maintaining enough fidelity to converge on good designs.

ML for Maintaining Obsolete Digital Systems

Mon, 06 Jan 2025 00:00:00 +0000

Overview

Computing systems in high-reliability deployments are often qualified for those deployments at system-level granularity while failures often occur at subsystem-level. Obsolescence poses a high risk to systems of this manner, as failing components often necessitate a complete system redesign or at least re-qualification, which is itself expensive and time-consuming. This project examines whether LLMs can be used to ease this burden by engineering drop-in replacements for failing, obsolete digital components based on the behavior of the original component and the broader design specifications of the system.

Applying Graph Algorithms for MoE Token Batching

Sun, 01 Sep 2024 00:00:00 +0000

Overview

Current LLMs often leverage Expert Parallelism to improve inference throughput. This poses challenges for routing tokens between physical devices while also batching effectively for throughput optimization, particularly for long context inputs. We applied a graph-based algorithm in this project and measured its effectiveness for routing tokens among physical devices assuming a model was deployed using expert parallelism.

Efficient Memory Access Monitoring and Bug Detection

Fri, 01 Sep 2023 00:00:00 +0000

Overview

Many existing tools for memory tracing and bug detection rely on dynamic program analysis. For this project, we implemented ideas presented in Spindle (Wang, et al.) to perform memory tracing and bug detection using static analysis, achieving constant execution time and trace size scaling with array element count compared to the increasing time and size scaling of tools like Intel Pin and Valgrind. Our implementation is available on GitHub at github.com/EECS-583-Group-4/final-project.git.

RTOS Driven Autonomous Vehicle

Mon, 22 Aug 2022 00:00:00 +0000

Overview

Developed an autonomous vehicle capable of navigating around a track of reflective tape using two simple light sensors using an FPGA board. The system implemented a MicroBlaze SoC on the FPGA and utilized the FreeRTOS Kernel for scheduling.

Exploration of Rowhammering Techniques

Tue, 18 Jan 2022 00:00:00 +0000

Overview

Conducted a survey of various techniques for rowhammering and their implementation schemes, then produced a report on how a synthesis of new techniques may be capable of breaking some of the finalists in the NIST PQC Standardization Process by serving as the fault-injection mechanism.

Power Usage of AES Power Analysis Attack Mitigation Strategies

Mon, 17 Jan 2022 00:00:00 +0000

Overview

Analyzed the power usage characteristics of a microcontroller performing AES encryptions across a variety of AES implementations. These implementations used many variations and combinations of masking and hiding techniques to improve their resiliency against power analysis attacks.